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I C bus transmission method
LV8498CT
2
Start and stop conditions
The I 2 C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a
data transfer operation.
SCL
SDA
ts2
th2
When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is
started when SDA is changed from high to low while SCL and SDA are high.
Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is
high.
SCL
SDA
Start condition
th1
Stop condition
th3
Data transfer and acknowledgement response
After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I 2 C bus, a
unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave
address and to the command (R/W) indicating the transfer direction of the subsequent data. However, this IC is provided
with only a write mode for receiving the data. Every time 8 bits of data for each byte are transferred, the ACK signal is
sent from the receiving end to the sending end. Immediately after the clock pulse of SCL bit 8 in the data transferred has
fallen to low, SDA at the sending end is released, and SDA is set to low at the receiving end, causing the ACK signal to be
sent. When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status,
the receiving end releases SDA at the falling edge of the ninth SCL clock.
Start
M
S
B
Slave address
L
S
B
W
A
C
K
M
S
B
Data
L
S
B
A
C
K
M
S
B
SCL
1st byte
2nd byte
SDA
A1 A2 A3 A4 A5 A6 A7 0
PD X D9 D8 D7 D6 D5 D4
L
S
B
A
C
K
M
S
B
Data
L
S
B
A
C
K
M
S
B
Data
L
S
B
A
C
K
Stop
SCL
3rd byte
4th byte
SDA
D3 D2 D1 D0 X X X X
ST2 ST1 ST0TM2TM1TM0
X X
T CARE
No.A1625-5/8
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